74112 Flip Flop JK with Preset and Clear

74LS112 TTL 74LS112 integrated circuit. Flip-flop J-K bistable negative T with clear and preset functions When the preset and clear functions are inactive (high), the data to the J and K inputs that meet the configuration time requirements are transferred to the outputs on the edge with negative slope of the clock pulse. Activation clock occurs at a voltage level and is not directly related to the clock pulse rise time. After the timeout interval, the data at inputs J and K can be changed without affecting the output levels. This versatile flip-flop can function as a bistable switch by binding J and K high. The 74S112 is characterized for operation from 0 to 70 ° C. Specifications

• Family: LS
• Flip-flop type: JK
• Shooting Type: Negative Edge
• Output Type: Differential / Complementary
• Minimum supply voltage: 4.75 V
• Maximum supply voltage: 5.25 V
• Propagation Delay: 15 ns
• Frequency: 30 MHz
• Output current: 8mA
• Minimum operating temperature: 0°C
• Maximum operating temperature: 70°C
• Encapsulated: Dip
• 16 pins