Description

74LS192 TTL 74LS192 Integrated Circuit, 4-bit synchronous BCD counters (dual clock having the complexity of 55 equivalent doors. Synchronous operation is provided with all Flip Flop synchronized simultaneously so that the outputs change matching to each other when instructed by direction logic This operation mode eliminates the output count peaks normally associated with asynchronous counters (wave clock).

The outputs of the four master slave switch failures are caused by a low to high transition of any input (clock) input. The counting address is determined by which count input is pressed while the other count input is high.

This counter is fully programmable; That is, each output can be preset to any of the levels by entering the desired data from the data inputs while the load input is low. The output will change to agree with the data inputs regardless of the counting pulses. This feature allows the counter to be used as a ndivisor module simply by modifying the count length with the preset entries.

A clear input has been provided that forces all outputs to the low level when a high level is applied. The erase function is independent of the count and load inputs. Clear, Count and Load inputs are cushioned to lower driving requirements. This reduces the number of clock drivers, etc., required for long words.

This device was designed to be cascaded without the need for external circuits. Both borrow and carry outputs are available to cascade both counting and down counting functions. The row output produces an equal pulse in width to the up-input count when an overflow condition exists.

The counter can be easily cascaded by feeding the loan and bringing outputs to the count down and counting the inputs, respectively, from the next counter.

Synchronous operation

Individual preset for each flip-flop

Specs