74165 Register 8 bits Parallel input Serial output

74LS165 The SN74LS165AN is an 8-bit parallel output offset register that shifts data in the QA direction to QH when it is registered. Parallel access to each stage is available through eight individual and direct data inputs that are enabled by a low level at the change/load input (SH/LD\). These logs also feature Synchronized Clock (CLK) inputs and complementary eighth bit outputs. All inputs are diode-supported to minimize transmission line effects, thus simplifying system design. Synchronization is done through a two-input NOR positive gate, allowing one input to be used as a clock inhibit function. Keeping High One of the clock inputs inhibits the clock and hold down any of the clock inputs with SH/LD\HIGH enables the other clock input. Clock inhibition (CLK INH) should be changed to the high level only while CLK is high. The parallel load is inhibited as long as SH/LD\ is high. The data in the parallel entries are loaded directly into the log.

COMPLEMENTARY EXITS

Direct override load inputs (data)

Clock inputs closed

Parallel to serial data conversion

Applications: Communications and Network

Specs

• Family: LS
• Output Type: Differential
• Logic type: scroll register
• Displacement Register Function: Parallel to Series
• Number of elements: 1
• Number of bits per element: 8
• Minimum supply voltage: 4.75 V
• Maximum supply voltage: 5.25 V
• Typical frequency: 35 MHz
• Dissipation power: 105 mW
• Minimum operating temperature: 0 ° C
• Maximum operating temperature: 70 ° C
• Encapsulated: Dip
• 16 pins
• Substitute
• NTE74165 NTE74LS165 NTE74HC165